* Wide Operating Range Embedded Clock SER/DES
— Up to 32-bit parallel LVCMOS data — 20 to 85 MHz parallel clock — Up to 2.72 Gbps application data paylod
* Select.
A built-in ATSPEED BIST feature validates link integrity and may be used for system diagnostics. — Dual Lane Mode (20 t.
The DS92LV3241 (SER) serializes a 32-bit data bus into 2 or 4 (selectable) embedded clock LVDS serial channels for a data payload rate up to 2.72 Gbps over cables such as CATx, or backplanes FR-4 traces. The companion DS92LV3242 (DES) deserializes th.
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